rggen 0.33.2
RgGen is a code generation tool for ASIC/IP/FPGA/RTL engineers. It will automatically generate source code related to control and status registers (CSR), e.g. SytemVerilog RTL, UVM RAL model, C header file, Wiki documents, from human readable register map specifications.
Gemfile:
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installieren:
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Runtime Abhängigkeiten (6):
rggen-c-header
~> 0.5.0
rggen-core
~> 0.33.0
rggen-default-register-map
~> 0.33.1
rggen-markdown
~> 0.26.0
rggen-spreadsheet-loader
~> 0.25.3
rggen-systemverilog
~> 0.33.0
Besitzer:
Pushed by:
Autoren:
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Taichi Ishitani
SHA 256-Prüfsumme:
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