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rggen 0.23.0

RgGen is a code generation tool for ASIC/IP/FPGA/RTL engineers. It will automatically generate soruce code related to configuration and status registers (CSR), e.g. SytemVerilog RTL, UVM RAL model, Wiki documents, from human readable register map specifications.

Versions:

  1. 0.23.0 - August 25, 2020 (8.5 KB)
  2. 0.22.0 - August 17, 2020 (8.5 KB)
  3. 0.21.1 - July 24, 2020 (8.5 KB)
  4. 0.21.0 - July 22, 2020 (8.5 KB)
  5. 0.20.0 - July 06, 2020 (8.5 KB)
Show all versions (39 total)

Runtime Dependencies (5):

Development Dependencies (1):

Owners:

Pushed by:

Authors:

  • Taichi Ishitani

SHA 256 checksum:

6633794cafa2fff848bc880ce685bfec132a5c6e1f181ee6b84ed6597517d992

Total downloads 23,551

For this version 136

Gemfile:
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install:
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License:

MIT

Required Ruby Version: >= 2.4

Links: