rggen 0.11.0

RgGen is a code generation tool for ASIC/IP/FPGA/RTL engineers. It will automatically generate soruce code related to control/status registers (CSR), e.g. SytemVerilog RTL, UVM RAL model, from human readable register map specifications.

Gemfile:
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安装:
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版本列表:

0.33.1 - January 23, 2024 (16.0 KB)
0.33.0 - January 22, 2024 (16.0 KB)
0.32.2 - January 03, 2024 (16.0 KB)
0.32.0 - December 28, 2023 (16.0 KB)
0.31.3 - October 18, 2023 (16.0 KB)
0.11.0 - August 11, 2019 (46.5 KB)

显示所有版本 (共 67 个)

Runtime 依赖 (3):

rggen-core ~> 0.11

rggen-spreadsheet-loader ~> 0.10

rggen-systemverilog ~> 0.11

Development 依赖 (1):

bundler >= 0

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业主:

推送:

作者:

Taichi Ishitani

SHA 256 校验和:

2dcc892f3b7e9c1419431299f4989ee3b3d5b0f21e057d738072f0ecdf328b00