rggen 0.33.4

RgGen is a code generation tool for ASIC/IP/FPGA/RTL engineers. It will automatically generate source code related to control and status registers (CSR), e.g. SytemVerilog RTL, UVM RAL model, C header file, Wiki documents, from human readable register map specifications.

Gemfile:
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installation:
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Versions:

0.33.4 November 28, 2024 (16 ko)
0.33.3 July 20, 2024 (16 ko)
0.33.2 June 11, 2024 (16 ko)
0.33.1 January 23, 2024 (16 ko)
0.33.0 January 22, 2024 (16 ko)

Voir toutes les versions (70)

Dépendances de Runtime (6):

rggen-c-header ~> 0.5.0

rggen-core ~> 0.33.1

rggen-default-register-map ~> 0.33.1

rggen-markdown ~> 0.26.0

rggen-spreadsheet-loader ~> 0.25.3

rggen-systemverilog ~> 0.33.1

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Propriétaires:

Pushed by:

Auteurs:

Taichi Ishitani

Total de contrôle SHA 256:

Total de téléchargements 102 861

Pour cette version 459

Version publiée:
November 28, 2024 2:07pm

License:
MIT

Version de Ruby requise: >= 3.0

New versions require MFA: true

Version published with MFA: true

Liens:

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