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rggen 0.35.2

RgGen is a code generation tool for ASIC/IP/FPGA/RTL engineers. It will automatically generate source code related to control and status registers (CSR), e.g. SytemVerilog RTL, UVM RAL model, C header file, Wiki documents, from human readable register map specifications.

Gemfile:
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Installeer:
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Versies:

  1. 0.35.2 July 21, 2025 (16 KB)
  2. 0.35.1 June 01, 2025 (16 KB)
  3. 0.35.0 February 19, 2025 (16 KB)
  4. 0.34.0 January 23, 2025 (16 KB)
  5. 0.33.4 November 28, 2024 (16 KB)
Toon alle versies (74 totaal)

Runtime afhankelijkheden (6):

rggen-c-header ~> 0.6.0
rggen-core ~> 0.35.1
rggen-default-register-map ~> 0.35.1
rggen-markdown ~> 0.27.0
rggen-spreadsheet-loader ~> 0.26.0
rggen-systemverilog ~> 0.35.1
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Eigenaren:

Pushed by:

Authors:

  • Taichi Ishitani

SHA 256 checksum:

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Total downloads 113.107

Voor deze versie 759

Versie vrijgegeven:

Licentie:

MIT

Required Ruby Version: >= 3.1

New versions require MFA: true

Version published with MFA: true

Links:

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