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rggen 0.34.0

RgGen is a code generation tool for ASIC/IP/FPGA/RTL engineers. It will automatically generate source code related to control and status registers (CSR), e.g. SytemVerilog RTL, UVM RAL model, C header file, Wiki documents, from human readable register map specifications.

Gemfile:
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install:
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Versions:

  1. 0.35.0 February 19, 2025 (16 KB)
  2. 0.34.0 January 23, 2025 (16 KB)
  3. 0.33.4 November 28, 2024 (16 KB)
  4. 0.33.3 July 20, 2024 (16 KB)
  5. 0.33.2 June 11, 2024 (16 KB)
Show all versions (72 total)

Runtime Dependencies (6):

rggen-c-header ~> 0.6.0
rggen-core ~> 0.34.0
rggen-default-register-map ~> 0.34.0
rggen-markdown ~> 0.27.0
rggen-spreadsheet-loader ~> 0.26.0
rggen-systemverilog ~> 0.34.0
Show all transitive dependencies

Owners:

Pushed by:

Authors:

  • Taichi Ishitani

SHA 256 checksum:

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Total downloads 104,866

For this version 338

Version Released:

License:

MIT

Required Ruby Version: >= 3.1

New versions require MFA: true

Version published with MFA: true

Links:

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