rggen 0.16.0

RgGen is a code generation tool for ASIC/IP/FPGA/RTL engineers. It will automatically generate soruce code related to control/status registers (CSR), e.g. SytemVerilog RTL, UVM RAL model, Wiki documents, from human readable register map specifications.

Gemfile:
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install:
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Versions:

0.33.3 July 20, 2024 (16 KB)
0.33.2 June 11, 2024 (16 KB)
0.33.1 January 23, 2024 (16 KB)
0.33.0 January 22, 2024 (16 KB)
0.32.2 January 03, 2024 (16 KB)
0.16.0 October 01, 2019 (8.5 KB)

Show all versions (69 total)

Runtime Dependencies (5):

rggen-core ~> 0.16

rggen-default-register-map ~> 0.16

rggen-markdown ~> 0.15

rggen-spreadsheet-loader ~> 0.14

rggen-systemverilog ~> 0.16

Development Dependencies (1):

bundler >= 0

Show all transitive dependencies

Owners:

Pushed by:

Authors:

Taichi Ishitani

SHA 256 checksum:

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Total downloads 99,642

For this version 1,786

Version Released:
October 1, 2019 8:30am

License:
MIT

Required Ruby Version: >= 2.3

New versions require MFA: true

Links:

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