origen_verilog 0.6.2

A parser and generator for Verilog (IEEE 1364)

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Versões:

0.6.3 - September 24, 2019 (117 KB)
0.6.2 - June 12, 2019 (117 KB)
0.6.1 - June 06, 2019 (117 KB)
0.6.0 - May 16, 2019 (117 KB)
0.5.2 - December 20, 2018 (117 KB)

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Runtime Dependencies (3):

ast ~> 2

origen >= 0.41.0

treetop >= 0

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Donos:

Autores:

Stephen McGinty

SHA 256 checksum:

1022ecc2af6549ffb7881609d97beed3469ead70baa469d5d3e3b9967c5ee54a