origen_verilog 0.2.0

A parser and generator for Verilog (IEEE 1364)

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Versões:

0.6.3 - September 24, 2019 (117 KB)
0.6.2 - June 12, 2019 (117 KB)
0.6.1 - June 06, 2019 (117 KB)
0.6.0 - May 16, 2019 (117 KB)
0.5.2 - December 20, 2018 (117 KB)
0.2.0 - December 13, 2017 (14,5 KB)

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Runtime Dependencies (2):

ast ~> 2

treetop >= 0

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Donos:

Autores:

Stephen McGinty

SHA 256 checksum:

85952b759c8c9095afbc7491271bbaad4fee915be2b78fa9ced6d61d73242b22