rggen 0.25.3
RgGen is a code generation tool for ASIC/IP/FPGA/RTL engineers. It will automatically generate soruce code related to configuration and status registers (CSR), e.g. SytemVerilog RTL, UVM RAL model, Wiki documents, from human readable register map specifications.
Gemfile:
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In die Zwischenablage kopieren
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installieren:
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Runtime Abhängigkeiten (5):
rggen-core
~> 0.25.1
rggen-default-register-map
~> 0.25.1
rggen-markdown
~> 0.21.0
rggen-spreadsheet-loader
~> 0.20.0
rggen-systemverilog
~> 0.25.1
Development Abhängigkeiten (1):
bundler
>= 0
Besitzer:
Pushed by:
Autoren:
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Taichi Ishitani
SHA 256-Prüfsumme:
a61e0825f3556e63bbe233fcf519bd03a791c255b47706880b66ef8c959cfc0c